...the world's most energy friendly microcontrollers
R_power
b0001
b0010
b0011
b0100
b0101
b0110
b0111
b1000
b1001
b1010 - b1111
Arbitrate after x DMA transfers
x=2
x=4
x=8
x = 16
x = 32
x = 64
x = 128
x = 256
x = 512
x = 1024
When N > 2 and is not an integer multiple of 2 then the controller always performs sequences of 2
transfers until N < 2 remain to be transferred. The controller performs the remaining N transfers at the
Note
You must take care not to assign a low-priority channel with a large R_power because this
prevents the controller from servicing high-priority requests, until it rearbitrates.
R R R
R
end of the DMA cycle.
You store the value of the R_power bits in the channel control data structure. See Section 8.4.3.3 (p.
53) for more information about the location of the R_power bits in the data structure.
8.4.2.2 Priority
When the controller arbitrates, it determines the next channel to service by using the following
information:
? the channel number
? the priority level, default or high, that is assigned to the channel.
You can configure each channel to use either the default priority level or a high priority level by setting
the DMA_CHPRIS register.
Channel number zero has the highest priority and as the channel number increases, the priority of a
channel decreases. Table 8.2 (p. 41) lists the DMA channel priority levels in descending order of
priority.
Table 8.2. DMA channel priority
Channel
number
0
1
2
3
4
5
6
7
0
Priority level
setting
High
High
High
High
High
High
High
High
Default
Descending order of
channel priority
Highest-priority DMA channel
-
-
-
-
-
-
-
-
2011-04-12 - d0001_Rev1.10
41
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